Semiconductor device

ABSTRACT

As devices are often different in the characteristics from one another, semiconductor chips based on the devices have discrepancies in the performance.  
     A semiconductor device having a semiconductor switching element and a drive controlling means ( 1 ) for generating from input signals (A) and (B) drive signals (a) and (b) to control the action of the semiconductor switching element is provided comprising a characteristic compensating means ( 2 ) for generating from a characteristic compensation input signal a compensation signal to eliminate variations in the transmission delay time of the drive controlling means ( 1 ).

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a circuit configuration in asemiconductor device and particularly to a circuit provided in a powermodule which has semiconductor switching elements of an insulating gatetype such as IGBTS, for trimming electrical characteristics of the powermodule.

DESCRIPTION OF THE RELATED ART

[0002]FIG. 13 illustrates a power module for an inverter circuit. Adrive controller circuit when receiving input signals UPin, VPin, WPin,UNin, VNin, and WNin supplies a group of IGBTs 1 to 6 with correspondingdrive signals UPout, VPout, WPout, UNout, VNout, and WNout (only UPoutand UNout shown in FIG. 13). While the power module shown in FIG. 13includes a single drive controller circuit provided for driving sixIGBTs, it may have two or more drive controller circuits.

[0003] Shown at the upper right of the drawing is a rectifier circuit ofsilicon bridge type for feeding the power module with a DC power. As aresistor Rs for current detection is installed in any emitter circuit ofthe IGBT2, it may produce a considerable level of current loss andpreferably installed in the second emitter circuit.

[0004]FIG. 14 is a timing chart showing input and output actions of theinput signals UPin and UNin. Denoted by t1 is a delay time taken fromthe inversion of the input signal UPin from high level to low level tothe inversion of the output signal UPout from low level to high level.As apparent from an output current Iup, the IGBT1 is switched on after adelay of time tonP. The delay time t1 of the former is attributed to thedrive controller circuit while the delay time tonP of the latter is aresponse time of the IGBT. More specifically, the IGBT1 is switched onafter a time tconP from the inversion of the input signal UPin from highlevel to low level.

[0005] Denoted by t2 is a delay time taken from the inversion of theinput signal UPin from low level to high level to the inversion of theoutput signal UPout from high level to low level. As apparent from anoutput current Iup, the IGBT1 is switched off after a delay time toffP.More particularly, the IGBT1 is switched off after a time tcoffP fromthe inversion of the input signal UPin from low level to high level.

[0006] Similarly, the IGBT2 is switched off after a timetcoffN(=t3+toffN) from the inversion of the input signal UNin from lowlevel to high level. The IGBT2 is switched on after a timetconN(=t4+tonN) from the inversion of the input signal UNin from highlevel to low level. As explicitly shown in FIG. 14, the output signalsUPout and UNout are inverted from their respective input signals UPinand UNin.

[0007] The delay times t1 to t4, tonp, toffP, toffN, and tonN are notuniform but varied depending on the drive controller circuit and theIGBTS. It is hence schemed for inhibiting the IGBT1 and the IGBT2 fromswitching on at the same time to have the off period of the IGBT2 setlonger than the on period of the IGBT1.

[0008] For the purpose, the high level duration of the input signal UNinhas to be set longer than the low level duration of the input signalUPin as shown in the drawing. This causes the input signal UNin tocontain an input cancel period (Tdead), thus allowing a higher level ofthe inverter control action with much difficulty.

[0009]FIG. 15 illustrates an over-current protection circuit provided inthe drive controller circuit shown in FIG. 13. As the sense resistor Rsconnected to the IGBT2 receives a current Irs, it produces a potentialVRs=Rs·Irs at one end. When the potential VRs exceeds a specific triplevel, the over-current protection circuit 3′ detects the generation ofshort-circuit and conducts its function of protection from short-circuitto stop the action of the drive controlling means 4′. However, theaction of the sense resistor may hardly be uniform while the trip leveldetermined by the over-current protection circuit 3′ is inconstant. Thiswill discourage the over-current protection thus providing inadequateprotection from the short-circuit.

[0010] Moreover, the greater the gradient of the current change at therise or fall of a corrector current of each IGBT, the more noises may beproduced. The smaller the gradient, the switching loss may be increased.There is a trade-off relationship between the generation of noises andthe increase of the switching loss. For compensation, each IGBT in theprior art has to be accompanied with its dedicated drive controllercircuit for enduring optimum driving conditions.

SUMMARY OF THE INVENTION

[0011] The present invention has been developed for eliminating theforegoing drawbacks and its object is to provide a semiconductor devicefor trimming the electrical characteristics of devices to eliminatediscrepancies between the devices thus enabling a higher level ofinverter controlling action, a semiconductor device for carrying out theshort-circuit protection and the over-temperature protection at higherprecision, and a semiconductor device for favorably determining thegradient at the rise and fall of the collector current of an outputdevice.

[0012] As a feature of the present invention defined in claim 1, asemiconductor device is provided comprising: a semiconductor switchingelement; a drive controlling means for controlling the action of thesemiconductor switching element with the use of an input signal; and acharacteristic compensating means for arbitrarily determining thetransmission delay time of the drive controlling means with the use of acharacteristic compensation input signal to eliminate discrepancies inthe delay time of the semiconductor switching element.

[0013] As another feature of the present invention defined in claim 2, asemiconductor device is provided comprising: a semiconductor switchingelement; a current detecting means for detecting the current flowingacross the semiconductor switching element; an over-current protectingmeans for canceling the action of the semiconductor switching elementwhen the detection signal from the current detecting means exceeds apredetermined trip level; and a characteristic compensating means formodifying the trip level.

[0014] As a further feature of the present invention defined in claim 3,a semiconductor device having a semiconductor switching element and adrive controlling means for controlling the action of the semiconductorswitching element based on an input signal is provided comprising acharacteristic compensating means for compensating the operationalcharacteristics of the semiconductor switching element through selectingand using one or more of driving devices which are provided in the drivecontrolling means and arranged different in the driving capability.

BRIEF DESCRIPTION OF THE DRAWING

[0015]FIG. 1 is a controller block diagram showing a first embodiment ofthe present invention;

[0016]FIG. 2 is a circuit diagram having shown the details of FIG. 1.

[0017]FIG. 3 is a timing chart of signals shown in FIG. 1;

[0018]FIG. 4 is a controller block diagram showing a second embodimentof the present invention;

[0019]FIG. 5 is a circuit diagram having shown the details of FIG. 4.

[0020]FIG. 6 is a timing chart of signals shown in FIG. 4;

[0021]FIG. 7 is a controller block diagram showing a third embodiment ofthe present invention;

[0022]FIG. 8 is a circuit diagram having shown the details of FIG. 7.

[0023]FIG. 9 is a timing chart of signals shown in FIG. 7;

[0024]FIG. 10 is a controller block diagram showing a fourth embodimentof the present invention;

[0025]FIG. 11 is a circuit diagram having shown the details of FIG. 10.

[0026]FIG. 12 is a timing chart of signals shown in FIG. 10;

[0027]FIG. 13 is a circuitry diagram showing a conventional powermodule;

[0028]FIG. 14 is a timing chart showing input and output actions shownin FIG. 13; and

[0029]FIG. 15 is a timing chart showing an action of protecting againstshort-circuits.

DETAILED DESCRIPTION OF THE PREFERRED EMBODYMENT

[0030] Embodiment 1

[0031]FIG. 1 is a controller block diagram showing the first embodimentof the present invention. A drive controller circuit 1 is responsive tothe input signals UPin and UNin from signal input terminals respectivelyfor delivering the output signals UPout and UNout to the gates of theIGBT1 and IGBT2 at the U phase which are connected in series between theoutput terminals P2 and N2 of the power module. FIG. 1 illustrates onlythe U phase although it contains identical circuits for driving theIGBT3 and IGBT4 at the V phase and the IGBT5 and IGBT6 at the W phase.

[0032]FIG. 2 shows a detailed circuit configuration of the drivecontroller circuit 1 and a characteristic compensator circuit 2. Thedrive controller circuit 1 includes a logic circuit 11 for convertingthe input signal UPin into a logic signal received by the line L1 of adelay interleave circuit 12. The delay interleave circuit 12 has threecapacitors C1, C2, and C3 connected with corresponding switches S1, S2,and S3 between the line L1 and the ground. The line L1 is supplied witha current 11.

[0033] The line L1 is connected via an inverter INV1 to the line L2 ofanother delay interleave circuit 13. Similarly, the delay interleavecircuit 13 has three capacitors C4, C5, and C6 connected withcorresponding switches S4, S5, and S6 between the line L2 and theground. The line L2 is supplied with a current 12. The line L2 isfurther connected via an inverter INV2 to a driver circuit 14. Thedriver circuit 14 feeds the IGBT1 with a driving signal UPout.

[0034] The capacitors C1, C2, C3, C4, C5, and C6 may be adaptedidentical or different in the capacitance. The number of the groupedcapacitors is not limited to three.

[0035] The characteristic compensator circuit 2 includes a write-incircuit 21 for writing a characteristic compensation signal into anEPROM 22 of which the data is then latched by a register 23. Theregister 23 generates and delivers latch data d1 to d6 as the drivingsignals to the corresponding switches S1 to S6. This allows the switchesS1 to S6 to be switched on and off desirably with the characteristiccompensation signal.

[0036] The action of the drive controller circuit 1 shown in FIG. 2 willnow be described referring to the timing chart shown in FIG. 3. Theinput signal UNin is different from that shown in FIG. 14 as having noinput cancel period (Tdead) and being precisely synchronized with theinput signal UPin which is inverted. Denoted by t11 is a delay timetaken from the inversion of the input signal UPin from high level to lowlevel to the inversion of the output signal UPout from low level to highlevel in the drive controller circuit 1. When the switches S1 to S3remain switched off, the delay time in the delay interleave circuit 12is zero and the delay time t11 is equal to the delay time t1 shown inFIG. 14.

[0037] Denoted by t12 is a delay time taken from the inversion of theinput signal UPin from low level to high level to the inversion of theoutput signal UPout from high level to low level in the drive controllercircuit 1. When the switches S4 to S6 remain switched off, the delaytime in the delay interleave circuit 33 is zero and the delay time t12is equal to the delay time t2 shown in FIG. 14.

[0038] While the drive controller circuit 1 shown in FIG. 2 illustratesone circuit for the input signal UPin, it actually includes otheridentical circuits (having the delay interleave circuits and thecharacteristic compensator circuit) for the input signals UNin, VPin,VNin, WPin, and WNin respectively. Hence, denoted by t13 is a delay timetaken from the inversion of the input signal UNin from low level to highlevel to the inversion of the output signal UNout from high level to lowlevel. Denoted by t14 is a delay time taken from the inversion of theinput signal UNin from high level to low level to the inversion of theoutput signal UNout from low level to high level. Those delay times mayarbitrarily be determined like t11 ad t12.

[0039] As its output signal UPout is inverted from low level to highlevel after the delay time t11 from the inversion of the input signalUPin from high level to low level, the IGBT1 is switched on after aperiod tonP (its response time). More particularly, the IGBT1 isswitched on after a period tconP from the inversion of the input signalUPin from high level to low level.

[0040] On the contrary, as its output signal UPout is inverted from highlevel to low level after the delay time t12 from the inversion of theinput signal UPin from low level to high level, the IGBT1 is switchedoff after a period toffP (its response time). More particularly, theIGBT1 is switched off after a period tcoffP from the inversion of theinput signal UPin from low level to high level.

[0041] Similarly, as its output signal UNout is inverted from high levelto low level after the delay time t13 from the inversion of the inputsignal UNin from low level to high level, the IGBT2 is switched offafter a period toffN (its response time). More particularly, the IGBT2is switched on after a period tcoffN from the inversion of the inputsignal UNin from low level to high level.

[0042] As its output signal UNout is inverted from low level to highlevel after the delay time t14 from the inversion of the input signalUNin from high level to low level, the IGBT2 is switched on after aperiod tonN (its response time). More particularly, the IGBT2 isswitched off after a period tconN from the inversion of the input signalUNin from high level to low level.

[0043] Even when the two input signals UPin and UNin are synchronizedwith each other as shown in FIG. 3, the delay time and the response timeof each IGBT are not uniform in the drive controller circuit 1 andtconP≠tcoffN is thus established. As a result, the switching on of theIGBT1 is not timed with the switching off of the IGBT2. Also, astcoffP≠tconN is established, the switching off of the IGBT1 is not timedwith the switching on of the IGBT2.

[0044] However, the delay time t11 or t13 can be adjusted by thecharacteristic compensation signal selecting the action of the switchesbetween

[0045] the switching off of all the switches,

[0046] the switching on of any one of the switches,

[0047] the switching on of any two of the switches, and

[0048] the switching on of all the switches. More practically, attconP≅tcoffN shown in FIG. 3, the IGBT1 can be switched on at the timingof switching off of the IGBT2. Similarly, as the delay times t12 and t14are adjusted to have tcoffP≅tconN, the IGBT1 can be switched off at thetiming of the switching on of the IGBT2.

[0049] When tconP≅tcoffN and tcoffP≅tconN are given, discrepancies inthe delay time including the response time of the drive controllercircuit 1 and the IGBTs can be eliminated in the entire arrangement ofthe device. This will require no use of the input cancel period (Tdead),thus allowing a higher level of the inverter controlling action.Alternatively, as the delay time is slightly drifted due todeterioration with time and temperature variation, the input cancelperiod Tdead may preferably be provided for offsetting the effect ofdrift. In that case, the period Tdead is too short as compared with thatin any prior art and will hardly disturb the highly advanced invertercontrolling action.

[0050] The EPROM 22 in the characteristic compensation circuit 2 may bea nonvolatile memory or one-time ROM. The characteristic compensationcircuit 2 may be installed in an integrated circuit form in the drivecontroller circuit 1.

[0051] Embodiment 2

[0052]FIG. 4 is a controller block diagram showing the second embodimentof the present invention. A drive controller circuit 4 comprises a logiccircuit 41 for transferring its input signal C as a logic signal and adriver circuit 42 arranged responsive to the logic signal for deliveringa drive signal c.

[0053] An over-current protection circuit 3 includes a comparator 31 ofwhich the non-inverting input terminal receives a voltage Vs developedat one end of a sense resistor Rs connected to the second emitter of theIGBT2. The reference voltage Vref is divided by the action of fourseries connected resistors into three components Vref1 to Vref3 whichare selectively connected as different trip levels to the invertinginput terminal of the comparator 31 by the action of three switches S1to S3. A signal output of the comparator 31 is transferred as adisconnection signal to the logic circuit 41.

[0054] A characteristic compensation circuit 5 is provided for switchingon any of the switches S1 to S3 and its circuit configuration isidentical to that of the characteristic compensation circuit 2 shown inFIG. 2. The characteristic compensation circuit 5 also includes an EPROMwhich may be a nonvolatile memory or one-time ROM. The characteristiccompensation circuit 5 may be implemented in an integrated circuit formin the drive controller circuit 4.

[0055] As described, the trip level or the emitter shunting ratiopredetermined in the sense resistor Rs and the over-current protectioncircuit 3 is varied between different units. This will discourage theover-current protection thus providing inadequate protection from theshort-circuit. The present invention allows the trip level to befavorably selected from Vref1, Vref2, and Vref3 on the basis of actualmeasurements, as shown in FIG. 6. As a result, the over-currentprotection can correctly be carried out. The number of the trip levelsfrom which the optimum is selected is not limited to three.

[0056] Embodiment 3

[0057]FIG. 7 is a controller block diagram showing the third embodimentof the present invention. FIG. 8 illustrates details of FIG. 7.Throughout FIGS. 7 and 8, like components are denoted by line numerals.An over-current protection circuit 7 is substantially identical in thearrangement to the over-current protection circuit 3. In particular, itscomparator 71 receives at the non-inverting input terminal a temperaturesignal Vt from a temperature sensing means 8.

[0058] When the temperature of the IGBT1 in operation increases and thetemperature signal Vt exceeds a predetermined trip level, thedisconnection signal is delivered to the drive controller circuit 4where the drive signal d generated from the input signal D is thusdisconnected. There are yet variations in the trip level forover-temperature protection and the measurement of the temperaturesensing means 8 in the over-current protection circuit 7, hencepermitting no precise over-temperature protection.

[0059] This embodiment allows the trip level to be favorably selectedfrom Vref1, Vref2, and Vref3, as shown in FIG. 9. As the trip level iscontrolled to an optimum setting from the actual measurements, theover-temperature protection can be carried out at higher precision.

[0060] Embodiment 4

[0061]FIG. 10 is a controller block diagram showing the fourthembodiment of the present invention. FIG. 11 illustrates details of FIG.10. A drive controller circuit 9 comprises a logic circuit 91 fortransferring an input signal E as a logic signal and a driver circuit92. Each of n-type FET transistors T1, T3, and T5 is connected at thedrain to the output terminal of the drive controller circuit 9. Theirgates can be connected by the action of corresponding switches S1, S3,and S5 to the output terminal of the logic circuit 91 or their ownsources.

[0062] Similarly, each of p-type FET transistors T2, T4, and T6 isconnected at the drain to the output terminal of the drive controllercircuit 9. Their gates can be connected by the action of correspondingswitches S2, S4, and S6 to the output terminal of the logic circuit 91or their own sources. The switches S1 to S6 are operated withcorresponding signals d1 to d6 received from a register provided in acharacteristic compensator circuit 10.

[0063] As timed with the fall of the input signal E, one of thetransistors T1, T3, and T5 connected to the output terminal of the logiccircuit 91 is driven. When the input signal E rises, one of thetransistors T2, T4, and T6 connected to the output terminal of the logiccircuit 91 is driven. The sum of current outputs of the driventransistors is released as a drive signal e.

[0064] This action is illustrated in the timing chart of FIG. 12. Adrive signal e1 is a combination of the outputs of the two transistorsT1 and T2. Also, a drive signal e2 is a combination of the outputs ofthe two transistors T3 and T4. As apparent, the combination of the twotransistors T3 and T4 is greater in the driving force than that of thetransistors T1 and T2. Accordingly, the drive signal e2 can be moremoderate at the rise and fall edges than the drive signal e1. Denoted by11 and 12 are corrector currents of the IGBT2 with the drive signals e1and e2 respectively.

[0065] In the prior art, the driving force of the drive controllercircuit has to be modified depending on the current capacity of eachIGBT. This embodiment allows the driver to be favorably selected from agroup of transistors having different driving capacities to determine anoptimum gradient at the rise or fall of the corrector current (output)of the IGBT2. Also, the characteristic compensator circuit 10 includesan EPROM which may be a nonvolatile memory or one-time ROM and may beinstalled in an integrated circuit form in the drive controller circuit9.

[0066] A set of the transistors to be driven is not limited to T1-T2,T3-T4, and T5-T6 but may be any pair such as T1-T4 or any combinationsuch as (T1+T3)-(T2+T4).

[0067] As defined in claim 2, the delay time of the semiconductorswitching elements is set to a desired length in the driver circuit toeliminate its discrepancies. Accordingly, the setting of input cancelperiod (Tdead) can be unnecessary and the inverter controlling actioncan be carried out at higher precision.

[0068] As defined in claim 3, the trip level used for judging theover-current can arbitrarily be determined to a desired setting, henceallowing a higher degree of the protection against short-circuits.

[0069] As defined in claim 5, the driver circuit includes a plurality ofdriving devices which are different in the current capacity so thatoptimum one can be selected from the driving devices. Accordingly, thegradient at the rise and fall of the corrector current of thesemiconductor switching element can arbitrarily be determined.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor switching element; a drive controlling means forcontrolling the action of the semiconductor switching elements based onan input signal; and a characteristic compensating means for arbitrarilydetermining the transmission delay time of said drive controlling meansbased on a characteristic compensation input signal to eliminatediscrepancies in the delay time of the semiconductor switching element.2. A semiconductor device comprising: a semiconductor switching element,a current detecting means for detecting the current flowing across thesemiconductor switching element; an over-current protecting means forcanceling the action of said semiconductor switching element when thedetection signal from the current detecting means exceeds apredetermined trip level; and a characteristic compensating means forcompensating said trip level.
 3. A semiconductor device having asemiconductor switching element and a drive controlling means forcontrolling the action of the semiconductor switching element, saidsemiconductor device comprising: a plarality of driving devices whichare provided in the drive controlling means and having different drivingcapability; selective means for selecting one or more driving devices;and a characteristic compensating means for compensating the operationalcharacteristics of the semiconductor switching element by the selectivemeans.
 4. The semiconductor device according to claim 1, wherein saidcharacteristic compensating means comprises at least one of anonvolatile memory memory or one-time ROM.
 5. The semiconductor deviceaccording to claim 2, wherein said characteristic compensating meanscomprises at least one of a nonvolatile memory memory or one-time ROM.6. The semiconductor device according to claim 3, wherein saidcharacteristic compensating means comprises at least one of anonvolatile memory memory or one-time ROM.
 7. The semiconductor deviceaccording to claim 4, wherein said at least one of a nonvolatile memoryor onetime ROM is provided in an integrated circuit form.
 8. Thesemiconductor device according to claim 5, wherein said at least one ofa nonvolatile memory or one-time ROM is provided in an integratedcircuit form.
 9. The semiconductor device according to claim 6, whereinsaid at least one of a nonvolatile memory or onetime ROM is provided inan integrated circuit form.